1. Field of the Invention
The present invention relates to an insulated electrical connection via connecting a front surface of a substrate to a single contact pad arranged on the rear side of the substrate, currently called via in the art.
2. Discussion of the Related Art
Among the many fields of use of vias, chip stack devices may be mentioned. In such devices, it is provided to superpose semiconductor wafers or chips above one another. This enables to increase the functions carried out by a device without increasing the occupied surface area.
In such devices, the connections between components of the different stages may be formed either by conventional wiring techniques, or by vias crossing the chip substrate.
An advantage of vias is the possibility of a collective manufacturing thereof, conversely to wires which must be assembled individually. The other main advantages of vias over wires are a surface gain, and the possibility of a surface distribution of the inputs/outputs. Another advantage of the connection by vias is that such vias will currently be made in silicon wafers. The silicon wafers will then assembled in various ways, among which that described hereafter, to be eventually diced into individual chips. Such collective methods provide cost reductions. In the present description, chip assemblies will be mentioned, but it should be clear that the chips may be wafers, semiconductor wafers or elements of semiconductor wafers.
FIGS. 1A and 1B are side cross-section views illustrating steps of a method for forming a solid via having a diameter smaller than 10 μm, for example, on the order of from 0.5 to 10 μm. FIG. 1C is a top cross-section view along plane C-C of FIG. 1B and shows a section of the formed via.
A thinned-down semiconductor wafer or chip W1 is superposed to a semiconductor wafer or chip W2. Chips W1 and W2 are for example bonded together by molecular bonding. The thinning down of chip W1 may be performed before or after the bonding. Chips W1 and W2 are each formed in a semiconductor substrate, according to conventional methods. They especially each comprise active areas, in which components are formed, and a stack of conductive interconnect tracks, for example, copper tracks, connecting the components together and to the inputs-outputs. At the surface of chip W2, on the surface side common to chips W1 and W2, a conductive contact pad 1 is provided, for example corresponding to a copper portion of an upper interconnect level. Contact pad 1 is connected to a terminal of the chip by conductive tracks, not shown, to be able to be connected to a reference voltage in a subsequent electrolytic deposition step.
A hole 3, thoroughly crossing the substrate of chip W1, is formed in front of contact pad 1. Hole 3 may be bored by dry etch or chemical etch. The walls of hole 3 are insulated, for example, by deposition of a silicon oxide layer 5. The portion of insulating layer 5 covering, at the bottom of hole 3, contact pad 1, is removed to leave access to pad 1.
The assembly thus formed is dipped into an adapted conductive electrolytic solution, for example copper sulfide. Contact pad 1 is set to a negative voltage and forms a cathode. A copper anode, connected to a positive voltage, is dipped into the electrolytic solution. A current thus flows between the anode and the cathode. Copper progressively deposits by electrolysis on the cathode, thus filling hole 3. The electrolysis is interrupted when hole 3 is full, thus forming a cylindrical via 7. A planarization step may further be provided to level the surface of via 7 after the electrolysis.
For diameters greater than a few μm, the forming of vias by electrolysis would be too long and too expensive to implement.
FIGS. 2A and 2B are side cross-section views illustrating steps of the forming of a hollow via having a diameter greater than 10 μm, for example, on the order of from 10 to 200 μm. FIG. 2C is a top cross-section via along plane C-C of FIG. 2B, and shows a cross-section of the formed via.
Semiconductor wafers or chips W1 and W2 are superposed as described hereabove. At the surface of chip W2, on the side of the surface common to chips W1 and W2, a conductive contact pad 11 is provided, for example corresponding to a copper portion of an upper interconnect level.
A hole 13 thoroughly crossing chip W1 is bored in front of pad 11. A sheath for insulating the walls of hole 13 is formed, for example, by deposition of a silicon oxide layer 15. The portion of insulating layer 15 covering contact pad 11 is removed to leave access to pad 11.
A conductive layer 17, for example, a copper layer, is formed by conformal deposition on the insulated walls and on the bottom of hole 13. Layer 17 forms a contact with pad 11 of chip W2.
The portions of layer 17 at the surface of chip W1 are removed to only keep the portion applied on the insulated walls and on the bottom of hole 13. The remaining portion of layer 17 thus forms a tubular via 17, which is ring-shaped in top view.
Via 17 is generally filled with a filling resin 19.
Tubular vias having diameters on the order of a few tens of μm, of the type described in relation with FIGS. 2A to 2C, are here considered.
In operation, when vias conduct currents, they generate heat by Joule effect. This results in a rise of their temperature, which may cause damage or a decrease in the chip lifetime.
Further, under the effect of temperature variations, resin 19 filling the vias is capable of deforming and of forming blisters.